1. Field of the Invention
The present invention relates to an electronic device and a method of fabricating the same, and more particularly, to the technique of packaging a device chip on a package substrate in flip-chip mounting.
2. Description of the Related Art
Conventionally, wire bonding is used to make mechanical and electrical connections between a chip of an electronic device and a package. In wire bonding, the device chip is mechanically connected to the package by an adhesive, and is electrically connected thereto by metal wires. Recently, the mainstream connection method is flip-chip bonding in which bumps are used to connect the chip and the package.
FIG. 12 shows a conventional art described in Japanese Patent Application Publication No. 2001-53577 (hereinafter simply referred to as Document 1) or Japanese Patent Application Publication No. 2001-110946 (Document 2). FIG. 12 shows a typical structure of an electronic device fabricated by flip-chip bonding. The electronic device has such a basic structure that bumps 2 are provided on a device chip 1 by using metal wires, and the device chip 1 with the bumps 2 is mounted on a wiring pattern 4 provided on a main surface of a ceramic package substrate 3 by a flip-chip bonder. The bumps 2 are bonded to the wiring pattern 4. This bonding makes mechanical and electrical connections between the device chip 1 and the package substrate 3. Then, a metal lid 10 is used to hermetically seal the device chip 1 in the final step of fabricating the electronic device. A seal solder layer 5 and a package-side seal pattern 6 are interposed between the package substrate 3 and the lid 10. The device 10 has a hollow portion 8, and an electrode pattern 9.
FIG. 13 shows another conventional art described in International Publication WO97/02596 (Document 3). The device chip 1 and the package substrate 3 are mechanically and electrically connected together in the same manner as that used for the device 10 shown in FIG. 12. Then, seal resin 11 is used to establish sealing and form an external shape so that the electronic device is completed.
FIG. 14 shows yet another conventional art described in Japanese Patent Application Publication No. 2004-129193 (Document 4). The device chip 1 and the package substrate 3 are mechanically and electrically connected together in the same manner as that used for the device shown in FIG. 12. During the process, the seal solder 5 are formed on the main surface of the package substrate 3 beforehand, and sealing is simultaneously performed. Then, the seal resin 11 is used to form the outer shape of the electronic device so that the electronic device is completed.
The conventional arts mentioned above that use flip-chip bonding to connect the device chip and the package substrate have a possibility that a foreign object may contact the electrode pattern 9 formed on the chip surface or moisture may enter into the contact so that the device does not function. Particularly, the above problem is serious to acoustic filters that use an elastic wave, such as surface acoustic wave (SAW) devices and film bulk acoustic resonators (FBARs). It is thus essential to hermetically seal the hollow region to protect the electrode pattern 9 from outside air.
However, the conventional arts have the respective drawbacks mentioned below. The device shown in FIG. 12 employs the metal lid 10 and the seal solder 5 to realize high hermetic seal and strong outer shape. However, the package substrate is required to have sidewalls, which prevents downsizing, reduced height and cost reduction of the device.
The device shown in FIG. 13 employs the seal resin 11, which may contribute to downsizing and height reduction. However, the device does not have good hermetic seal and comparatively low reliability. Further, the device may be liable to be affected by external waves because the entire chip is not shielded by metal. Particularly, poor shield may cause degraded performance of high-frequency (RF) components.
The device shown in FIG. 14 may overcome the drawbacks of the conventional devices shown in FIGS. 12 and 13 and is characterized in that the chip is sealed with the seal solder layer 5, and is then sealed with the resin 11. However, the device uses the two different materials for sealing and forming the outer shape, and has a problem in terms of the cost. It is also required to form the seal solder layer on the package substrate beforehand. This may produce devices having errors in shape and limit the time for thermal treatment. Mass productivity may be improved by flip-chip mounting chips on a sheet-shaped multi-production substrate and by simultaneously performing soldering. In this process, the whole sheet-shaped substrate is inevitably heated up to 300° C. or higher for a couple of minutes. This thermal treatment causes the metal layer mounted on the device chip and the package substrate and adapt to solder to be melted in solder, and degrades the reliability.